Please referring to FIG. 1, it is a drawing schematically showing a pixel cell of a thin film transistor of a LCD panel (hereinafter referred to as LCD) in accordance with an existing technology. The pixel cell 100 comprises a switching transistor Qd, a liquid crystal capacitor Clc, and a storage capacitor Cs. Furthermore, the gate of the switching transistor Qd is connected to the gate line Gn, the drain of the switching transistor Qd is connected to the source line Sn, and the storage capacitor Cs and the liquid crystal capacitor are connected the source of the switching transistor Qd.
As is well known, the gate line Gn of the LCD is connected to a gate driver. When the gate driver generates a gate pulse (gate pulse), the switching transistor Qd will be opened and the source driver can input the corresponding video voltage through the source line Sn to the pixel cell 100. Furthermore, the high voltage in the gate pulse of the gate driver can be used to turn on the switching transistor Qd, wherein the high voltage is called as a high gate voltage (VGH); while the low voltage in the gate pulse of the gate driver can be used to turn off the switching transistors Qd, wherein the low voltage is called as a low gate voltage (VGL).
Generally speaking, when the switching transistor Qd is turned off, a feed-through phenomenon would be generated due to a voltage Vgs on a parasitic capacitance Cgs between the gate and the source of the switching transistor. While, the high gate voltage (VGL) is critical to determine whether the feed-through phenomenon is serious, and when the feed-through phenomenon is lighter, flicker on the LCD panel would also be reduced.
Furthermore, the higher the high gate voltage (VGH) is, the faster the speed of the video voltage on the source line Sn 100 charging the pixel cell 100 would, but the more serious the feed-through phenomenon would be. Therefore, in order to take into account both of the charging efficiency of the video voltage and the feed-through phenomenon, output pulse of the current gate driver would be processed on the high gate voltage (VGH), resulting in a gate pulse with cutting edge waveform. In other words, the gate pulse with cutting edge waveform is generated by means of reducing the high level voltage before a falling edge of the gate pulse, to thereby reduce a voltage drop of the gate pulse at the falling edge and reduce feed-through phenomenon.
Please refer to FIG. 2A and FIG. 2B, they are diagrams showing a variation of gate driving voltage on the gate line. What as shown in FIG. 2A is a gate pulse (VGn) having its waveform without cutting edge. That is, at the moment the transistor Qd is turned off, the voltage Vgs (Va1-Va2) on the parasitic capacitance Cgs is great, thus resulting in a large feed-through phenomenon. What as shown in FIG. 2B is a gate pulse (VGn) with a waveform including a cutting edge. That is, at the moment the transistor Qd is turned off, the voltage (Vb1-Vb2) on the parasitic capacitance Cgs is smaller, thus reducing the feed-through phenomenon. In other words, early drop of the high gate voltage (VGH) can make the gate pulse waveform including cutting edge and allow the parasitic capacitance Vgs to slowly decrease the voltage during a time period t, and the longer the time period t lasts for, the lower the feed-through phenomenon is.
Please referring to FIG. 3A and FIG. 3B, they are diagrams showing gate pulse modulating circuit and associated signals thereof, in accordance with an existing technology. A gate pulse modulating circuit 300 comprises a timing controller 310, a high gate voltage generating unit 320, a low gate voltage generating unit 330, and a gate driver 340.
In order to achieve a high gate voltage (VGH) with a waveform including a cutting edge, the timing controller 310 outputs a time control signal T1 to the high gate voltage generating unit 320, enabling the high gate voltage generating unit 320 to output a high gate voltage (VGH). Furthermore, the low gate voltage generating unit 330 outputs a low gate voltage (VGL). The gate driver 340 receives the output enable signal (OE) from the timing controller 310, the high gate voltage (VGH), and the low gate voltage (VGL), and generates multiple gate pulses (G1˜Gn) to the corresponding gate lines.
As shown in FIG. 3, the high gate voltage (VGH) outputted by the high gate voltage generating unit 320 is controlled by the timing controller 310 and thereby begins to drop from 23V at a particular time point. The low gate voltage (VGL) outputted from the low gate voltage generating unit 320 would be maintained steadily at −10V. Of course, the above-mentioned parameters, such as 23V of the high gate voltage (VGH) and −10V of the low gate voltage (VGL) are just examples, and not limited to the actual voltage values of the high gate voltage (VGH) and the low gate voltage (VGL).
Furthermore, the output enable signal (OE) outputted from the timing controller 310 is used to control the gate driver 340 to generate the gate pulses. As shown in FIG. 3B, in the first time period of high level of the output enable signal (OE), the high gate voltage (VGH) outputted from the high gate voltage generating unit 320 is converted by the gate driver 340 to a first gate pulse (G1) on the first gate line; while at the rest of the time a low gate voltage (VGL) is maintained on the first gate line. Similarly, in the second time period of high level of the output enable signal (OE), the high gate voltage (VGH) outputted from the high gate voltage generating unit 320 is converted by the gate driver 340 to a second gate pulse (G2) on the second gate line; while at the rest of the time a low gate voltage (VGL) is maintained on the second gate line. In the third time period of high level of the output enable signal (OE), the high gate voltage (VGH) outputted from the high gate voltage generating unit 320 is converted by the gate driver 340 to a third gate pulse (G3) on the third gate line; while at the rest of the time a low gate voltage (VGL) is maintained on the third gate line. In the fourth time period of high level of the output enable signal (OE), the high gate voltage (VGH) outputted from the high gate voltage generating unit 320 is converted by the gate driver 340 to a fourth gate pulse (G4) on the fourth gate line; while at the rest of the time a low gate voltage (VGL) is maintained on the fourth gate line. And so on produce multiple gate pulses.
Obviously, the time control signal T1 generated by the timing controller 310 is used to control the high gate voltage generating unit 320, enabling the high gate voltage generating unit 320 to generate the high gate voltage (VGH) in response to the time control signal, and thereby enabling the gate driver 340 to output the gate pulses (G1—Gn) with a waveform including a cutting edge.
Please refer to FIG. 4A and FIG. 4B, they are diagrams showing a high gate voltage generating unit and signals of a gate pulse modulating circuit, in accordance with an existing technology. The high gate voltage generating unit 320 comprises an inverter INV, a P-type transistor Q1, an N-type transistor Q2, a resistor Radj, and a capacitor Cg. Among them, the input of the inverter INV receives the time control signal T1, and the output of the inverter INV is connected to the gates of the P-type transistor Q1 and the N-type transistor Q2. The source of the P-type transistor Q1 is connected to a power source terminal Vcc, the drain of the P-type transistor Q1 is connected to the drain of the N-type transistor Q2 drain, and the a resistor Radj is connected between the source of the N-type transistor Q2 source and the ground. The capacitor Cg is connected between the drain of the P-type transistor Q1 and the ground, and the drain of the P-type transistor Q1 drain can produce the high gate voltage (VGH).
Known from the time control signal T1 and the high gate voltage (VGH) in FIG. 4B, at the time point t2 the time control signal T1 is at a low level, the N-type transistor Q2 is turned on and the P-type transistor Q1 is turned off, the N-type transistor Q2 and the resistor Radj generate a discharging path. Therefore, the voltage on the capacitor Cg drops from the Vcc, that is, the high gate voltage (VGH) drops. At the time point t4, the time control signal T1 is at a high level, the N-type transistor Q2 is turned off and the P-type transistor Q1 is turned on, the P-type transistor Q2 generates a charging path. Therefore, the voltage on the capacitor Cg is charged to Vcc, that is, the high gate voltage (VGH) returns to Vcc.
Apparently, the resistance value of the discharging path is greater than the resistance value of the charging path. Therefore, charging speed is faster than the discharging speed. Similarly, at the time points t2′ and t4′, and at the time points t2″ and t4″, the variation of high gate voltage (VGH) is same to the variation at the time points t2 and t4, and not be repeated here.
The relationship between the output enable signal OE generated by the timing controller 310 and the time control signal T1 can be known in FIG. 4B. At the time point t1, the output enable signal OE has a level transition; at the time point t2, the time control signal T1 has a level transition; at the time point t3, the output enable signal OE has a level return; at the time point t4, the time control signal T1 has a level return. Therefore, in an enable period (t1˜t3{grave over ( )}t1′˜t3′{grave over ( )}t1″˜t3″) when the output enable signal OE is at the high level, the high gate voltage (VGH) is converted by the gate driver 340 to the gate pulses (G1, G2, G3).
In order to reduce the LCD screen flicker, it is known to use the gate pulse with a waveform including a cutting edge to reduce the feed through phenomenon. However, that gate pulse with a waveform including a cutting edge consumes more energy. The above technology is applied to the LCD panels having a half source driving (HSD) structure, energy consume is more serious because of doubling number of the gate.